The invention relates to chemical mechanical planarization (CMP) of semiconductor wafer materials and, more particularly, to CMP compositions and methods for removing barrier materials of semiconductor wafers in the presence of underlying dielectrics.
Typically, a semiconductor wafer has a wafer of silicon and a dielectric layer containing multiple trenches arranged to form a pattern for circuit interconnects within the dielectric layer. The pattern arrangements usually have a damascene structure or dual damascene structure. A barrier layer covers the patterned dielectric layer and a metal layer covers the barrier layer. The metal layer has at least sufficient thickness to fill the patterned trenches with metal to form circuit interconnects.
CMP processes often include multiple planarization steps. For example, a first step removes a metal layer from underlying barrier dielectric layers. The first step polishing removes the metal layer, while leaving a smooth planar surface on the wafer with metal-filled trenches that provide circuit interconnects planar to the polished surface. First step polishing steps tend to remove excess interconnect metals, such as copper at an initial high rate. For example, Lee et al., in EP Pat. Pub. No. 1 072 662 A1, disclose the use of guanidine as an abrasion accelerator for accelerating an abrasive composition's dielectric removal rate. After the first step removal, the second step polishing can remove a barrier that remains on the semiconductor wafer. This second step polishing removes the barrier from an underlying dielectric layer of a semiconductor wafer to provide a planar polished surface on the dielectric layer.
Unfortunately, CMP processes often result in the excess removal of unwanted metal from circuit interconnects or dishing. This dishing can result from, both first step polishing, and second step polishing. Dishing in excess of acceptable levels causes dimensional losses in the circuit interconnects. These “thin” areas in the circuit interconnects attenuate electrical signals and impair continued fabrication of dual damascene structures.
A barrier typically is a metal, metal alloy or intermetallic compound, such as tantalum or tantalum nitride. The barrier forms a layer that prevents migration or diffusion between layers within a wafer. For example, barriers prevent the diffusion of interconnect metal such as copper or silver into an adjacent dielectric. Barrier materials must be resistant to corrosion by most acids, and thereby, resist dissolution in a fluid polishing composition for CMP. Furthermore, these barrier materials may exhibit a toughness that resists removal by abrasion abrasive particles in a CMP slurry and from fixed abrasive pads.
Erosion refers to unwanted recesses in the surface of dielectric layers that result from removing some of the dielectric layer by the CMP process. Erosion that occurs adjacent to the metal in trenches causes dimensional defects in the circuit interconnects. These defects contribute to attenuation of electrical signals transmitted by the circuit interconnects and impair subsequent fabrication of a dual damascene structures in a manner similar to dishing. The removal rate of the barrier, versus, a removal rate of the metal interconnect or the dielectric layer is known as the selectivity ratio.
Most barrier materials are difficult to remove by CMP, because the barrier materials resist removal by abrasion and by dissolution. Typical barrier removal slurries require a high abrasive concentration, such as at least 7.5 weight percent, in a fluid polishing composition to remove a barrier material. But slurries having these high abrasive concentrations tend to provide detrimental erosion to the dielectric layer and result in dishing, erosion and scratching of the copper interconnect. In addition to this, high abrasive concentrations can result in peeling or delaminating of low-k dielectric layers from semiconductor wafers.
There is an unsatisfied demand for an improved CMP composition for selectively removing tantalum barrier materials. In particular, there is a need for a CMP composition for selectively removing tantalum barrier materials with reduced dielectric erosion and reduced dishing, erosion and scratching of the metal interconnect. Furthermore, there is a desire to remove tantalum barrier materials without peeling low-k dielectric layers from semiconductor wafers.